Replacement Gate ETSOI with Sharp Junction

ABSTRACT

A transistor structure includes a channel disposed between a source and a drain; a gate conductor disposed over the channel and between the source and the drain; and a gate dielectric layer disposed between the gate conductor and the source, the drain and the channel. In the transistor structure a lower portion of the source and a lower portion of the drain that are adjacent to the channel are disposed beneath and in contact with the gate dielectric layer to define a sharply defined source-drain extension region. Also disclosed is a replacement gate method to fabricate the transistor structure.

TECHNICAL FIELD

The exemplary embodiments of this invention relate generally tosemiconductor devices and fabrication techniques and, more specifically,relate to the fabrication of semiconductor transistor devices, such asfield effect transistors (FETs) used in random access memory (RAM) andlogic circuitry, using an extremely thin silicon on insulator (ETSOI)substrate, also referred to as a fully-depleted silicon on insulator(FDSOI) substrate.

BACKGROUND

In silicon on insulator (SOI) technology a thin silicon layer is formedover an insulating layer, such as silicon oxide, which in turn is formedover a bulk substrate. This insulating layer is often referred to as aburied oxide (BOX) layer or simply as a BOX. Sources and drains of fieldeffect transistors (FETs) are formed by the addition of N-type and/orP-type dopant material into the thin silicon layer, with a channelregion being disposed between the source and drain.

SUMMARY

In accordance with the exemplary embodiments of this invention there isprovided a transistor structure that comprises a channel disposedbetween a source and a drain; a gate conductor disposed over the channeland between the source and the drain; and a gate dielectric layerdisposed between the gate conductor and the source, the drain and thechannel. In the structure the source and the drain are a raisedsource-drain and a lower portion of the source and a lower portion ofthe drain that are adjacent to the channel are disposed beneath and incontact with the gate dielectric layer to define a source-drainextension region.

Further in accordance with the exemplary embodiments of this inventionthere is provided a method to fabricate a structure. The method includesproviding a wafer comprising a semiconductor substrate having a topsurface, an insulating layer disposed over the top surface and asemiconductor layer disposed over the insulating layer. The methodfurther includes forming on the semiconductor layer a sacrificial gatestructure that overlies a sacrificial insulator layer; forming a raisedsource and a raised drain on the semiconductor layer adjacent to thesacrificial gate structure; depositing a layer that covers the raisedsource and the raised drain and that surrounds the sacrificial gatestructure; removing the sacrificial gate structure leaving an opening inthe layer that extends to the sacrificial insulator layer; selectivelyremoving a portion of the layer to widen the opening in the oxide layerso as to expose some but not all of the raised source and the raiseddrain that are adjacent to the exposed semiconductor layer. In thismethod selectively removing also removes the sacrificial insulator layerto expose the underlying semiconductor layer. The method furtherincludes forming a spacer layer on sidewalls of the opening, the spacerlayer covering only an upper portion of the exposed raised source andthe raised drain, leaving still exposed a lower portion of the raisedsource and raised drain that are adjacent to the exposed semiconductorlayer. The method further includes depositing a layer of gate dielectricmaterial within the opening so as cover the spacer layer, the exposedportion of the semiconductor layer, and the exposed lower portion of theraised source and the raised drain; and depositing a gate conductorwithin the opening and over the layer of gate dielectric material.

Still further in accordance with the exemplary embodiments of thisinvention there is provided an integrated circuit comprising a pluralityof transistors. Each of the transistors is comprised of a channeldisposed in a layer of silicon and disposed between a raisedsource-drain structure, a gate conductor disposed over the channel andbetween the source and the drain and a gate dielectric layer disposedbetween the gate conductor and the source, the drain and the channel.The raised source drain structure comprises a source facet and a drainfacet that upwardly slope away from channel. An area of the lowerportion of the facet of the source and the facet of the drain that arecovered by the gate dielectric layer define a source-drain extensionregion, where the area of the lower portion of the facet of the sourceand the facet of the drain is selected to optimize a tradeoff betweencapacitance and resistance of the source-drain extension region.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIGS. 1-7 each present a cross-sectional enlarged view (not to scale) ofa portion of an ETSOI wafer and depict the execution of sequentiallyperformed transistor processing and fabrication steps.

FIG. 8A shows the fabrication of a gate dielectric and gate metal in thestructure formed by the process of FIGS. 1-7, while FIG. 8B is anenlarged view of a portion of the structure shown in FIG. 8B. FIGS. 8Aand 8B may be collectively referred to as FIG. 8.

FIG. 9 shows a block diagram of an exemplary design flow used forexample, in semiconductor IC logic design, simulation, test, layout, andmanufacture.

DETAILED DESCRIPTION

ETSOI has become a viable device option for continued scaling of CMOStechnology. One challenge for fabricating ETSOI is to achieve a sharpjunction and low extension resistance. It is desirable to provide asharp, well-defined junction to achieve good short-channel control. Asharp junction can be formed by implantation of a suitable dopantspecies. However, implantation tends to damage the ETSOI layer and canresult in an increased extension resistance. The junction can also beformed by a thermally-driven diffusion of dopant species which avoidsdamaging the ETSOI layer. However, the diffusion process can bedifficult to control to achieve the desired sharp, well-definedjunction.

The exemplary embodiments of this invention provide a method for formingan ETSOI device (e.g., a FET device) with a sharp junction and a lowextension resistance through the use of a replacement gate process. Theembodiments of this invention also encompass a structure that isfabricated in accordance with the method.

FIG. 1 shows an enlarged cross-sectional view of a small portion of astarting wafer structure 10. The wafer structure 10 includes asemiconductor (e.g., Si) substrate 12, an electrically insulating layerwhich can be referred to as a buried oxide (BOX) layer 14 and a thin Sitop layer, also referred to as an ETSOI layer 16 or simply as an ETSOI.The substrate 12 can be, for example, a p-type Si substrate and can haveany suitable thickness. The BOX 14 can have a thickness in a range of,by example, about 10 nm to about 200 nm. The ETSOI layer 16 can have athickness in a range of about 5 nm to about 12 nm, with about 6 nm-7 nmbeing a suitable thickness for many applications of interest.

FIG. 2 shows a thin oxide layer 18 that is grown over the ETSOI layer 16(dummy gate oxide layer) and a dummy gate structure 20 that is formedatop the oxide layer 18. The oxide layer 18 may have a thickness in arange of about 1 nm to about 10 nm and may be a layer of SiO₂. The dummygate structure 20 can be formed of silicon nitride (Si₃N₄) and can havea thickness in a range of about 25 nm to about 100 nm, or morepreferably in a range of about 30 nm to about 70 nm, and a width in therange of about 15 nm to about 35 nm. As will be made apparent below boththe oxide layer 18 and the dummy gate structure 20 are sacrificialstructures that are subsequently removed during processing. Before it isremoved the oxide layer 18 will form an etch stop layer during asubsequent processing step shown in FIG. 5.

FIG. 3 shows a result of the formation of raised source/drain (RSD)structures 22A, 22B. The RSD structures 22A, 22B are preferably in-situdoped and may have a dopant atom concentration in a range of, forexample, about 5×10²⁰/cm³ to about 8×10²¹/cm³. The RSD structures 22A,22B are formed by the epitaxial growth of silicon, such as by the use ofa mixture of silane and dichlorosilane gases with a chemical vapordeposition (CVD) process. Phosphorus is one suitable n-type dopant, andBoron is one suitable p-type dopant. The epitaxial growth ispreferential to Si and results, possibly in combination with an etchingstep performed during a cyclical epitaxial growth process, in a layerthat exhibits facets 23A and 23B adjacent to the dummy gate 20.

The formation of in-situ doped RSD structures is well characterized inthe art. For example, reference can be made to commonly owned U.S. Pat.No. 6,774,000, “Method of Manufacture of MOSFET Device with In-SituDoped Raised Source and Drain Structures”, Wesley C. Natzle et al., andto “A raised source/drain technology using in-situ P-doped SiGe andB-doped Si for 0.1-μm CMOS ULSIs”, Takashi Uchino et al., ElectronDevices meeting, 1997, IEDM '97. Technical Digest, International, 7-10Dec. 1997, pgs. 479-482. Reference can also be made to “Extremely ThinSOI (ETSOI) CMOS with Record Low Variability for Low PowerSystem-on-Chip Applications”, K. Cheng, A. Khakifirooz, P. Kulkarni, S.Ponoth, J. Kuss, D. Shahrjerdi, L. F. Edge, A. Kimball, S.Kanakasabapathy, K. Xiu, S. Schmitz, A. Reznicek, T. Adam, H. He, N.Loubet, S. Holmes, S. Mehta, D. Yang, A. Upham, S.-C. Seo, J. L. Herman,R. Johnson, Y. Zhu, P. Jamison, B. S. Haran, Z. Zhu, L. H. Vanamurth, S.Fan, D. Horak, H. Bu, P. J. Oldiges, D. K. Sadana, P. Kozlowski, D.McHerron, J. O'Neill, B. Doris, Solid-State Circuits Conference Digestof Technical Papers (ISSCC), 2010 IEEE International Issue Date: 7-11Feb. 2010 pgs. 152-153.

FIG. 4 shows a result of the deposition and subsequent planarization ofa layer 24 (e.g., an oxide layer such as SiO₂). The layer 24 may begrown initially to a thickness that is about twice that of the dummygate structure 20. A chemical mechanical polish (CMP) process is thenused to planarize the layer 24, with the CMP process stopping on thenitride dummy gate structure 20.

Note that in some embodiments the layer 24 could be a nitride layer(e.g., Si₃N₄).

FIG. 5 shows a result of the selective removal of the dummy gatestructure 20 to leave an opening 26 in the layer 24 that extends to thedummy gate oxide layer 18. Assuming that the dummy gate sstructure 20 iscomposed of silicon nitride (Si₃N₄) then any suitable wet or dry etchprocess for removing the nitride can be used. Preferably the process isselective to Si and Si0 ₂ so as to remove only the nitride “plug” thatformed the dummy gate structure 20. For example, the dummy gatestructure 20 can be removed using hot phosphoric acid (e.g., heated to atemperature of about 160° C. or greater) and/or a dry plasma etchprocess can be used.

FIG. 6 shows a result of an oxide etch process that selectively removesthe dummy gate oxide 18 and that also serves to enlarge the width of theopening 26, forming an enlarged opening 26A. The opening 26 is enlargedat each sidewall by what may be referred to for convenience as an oxidepull-back (PB) dimension. The PB dimension may be in a range of about0.5 nm to about 6 nm. It can be noted that at this point in theprocessing the ETSOI is exposed as is a lower portion of the RSD 22adjacent to the ETSOI. A chemical oxide removal process (COR) can beused to selectively remove only the oxide. Reference with regard to CORcan be made to Natzle, W., Horak, D., Deshpande, S., Yu, C., Liu, J.,Mann, R., Doris, B., et al. (2004), “Trimming of hard-masks by gaseousChemical Oxide Removal (COR) for sub-10 nm gates/fins, for gate lengthcontrol and for embedded logic”, Advanced Semiconductor Manufacturing2004 ASMC 04 IEEE Conference and Workshop (pp. 61-65). As is stated inthis publication, basically the COR process is a gaseous,plasma-free/damage-free etch process that uses a mixture of HF and NH₃in a ratio of approximately 2:1. Reaction is carried out at pressuresbelow 15 m Ton at 25° C. to form solid ammonium hexafluorosilicate,followed by evaporation at a temperature greater than 100° C.

Note that if the layer 24 is a nitride layer the COR process can stillbe used, although it will typically proceed at a slower rate than if thelayer 24 is an oxide layer.

FIG. 7 shows a result of a deposition of a conformal silicon nitride(Si₃N₄) layer followed by an anisotropic ion etch that removes theconformal nitride layer from all horizontal surfaces (those surfacesnormal or about normal to the etchant ion stream). The anisotropic etchleaves an inner silicon nitride spacer 28 on sidewalls of the opening26A. Note that the ETSOI 16 at the bottom of the opening is exposed,which eventually will function as the channel of the resultant FETdevice, as is a lower portion 21 of the RSD 22 facet adjacent to theETSOI.

FIG. 8A shows a result of a deposition of a high dielectric constant(high-k), as compared to SiO₂, gate insulator layer 30 (e.g., thicknessin a range of about 1 nm to about 3 nm) followed by deposition of ametal gate 32 to fill the opening 26A. The high-k gate insulator 30 maybe any suitable material such as, but not limited to, hafnium silicate,zirconium silicate, hafnium dioxide and zirconium dioxide. Thesematerials can be deposited using atomic layer deposition (ALD). Themetal gate 32 can be formed of any suitable electrically conductive gatematerial including titanium nitride, aluminum nitride and tantalumnitride, as non-limiting examples. Note that in other embodiments thegate structure could be formed to include other materials such as anoxynitride for the gate insulator and polysilicon for the gateconductor.

Reference is also made to FIG. 8B for showing an enlarged view of aportion of the structure shown in FIG. 8A. It can be seen that theportion 21 (an overlap portion or region) of the RSD 22 adjacent to theETSOI is covered by the high-k layer 30 and the overlying metal gate 32.This overlap region defines a source-drain extension 34 and ischaracterized by a sharp and abrupt junction having reduced resistance(Rext). The source-drain extension 34 so formed avoids the ETSOI damagethat can occur during an extension implant process, and furthermore ismuch more sharply defined than would be the case if the extension wereformed by a thermally-driven dopant diffusion process.

The processing can also include a thermal diffusion step to drivedopants into the ETSOI layer underneath the RSD. Since theextension-gate overlap region is determined by the size of the gate holeand the inner spacer, the thermal diffusion process can be significantlyreduced compared to the prior art case. A requirement of the dopingprofile in the RSD/ETSOI structure is that the dopants butt the buriedoxide BOX 14.

The teachings of this invention can also be applied in the case ofconventional Bulk/PDSOI or FinFET Tri Gate devices, where an in-situdoped RSD extension and replacement gate is used.

The area of the overlap portion or region 21 of the RSD 22 adjacent tothe ETSOI, that is in contact with the high-k layer 30 and thatunderlies the metal gate 32, is preferably sized as a trade-off betweencapacitance and resistance. In general, the larger the area the higherwill be the capacitance and the lower will be the resistance.Conversely, the smaller the area the lower will be the capacitance andthe higher will be the resistance. One desirable goal is to achieve avalue of capacitance and resistance that accommodates a desired minimumtransistor turn-on and turn-off time (switching speed).

Processing (not illustrated) continues so as to form the neededsource/drain and gate contact metallization and any other desired andconventional processes in order to complete the fabrication of the FET.

The various dopants and doping concentrations, layer thicknesses andspecific materials discussed above are exemplary and can vary from thosespecifically described and shown.

FIG. 9 shows a block diagram of an exemplary design flow 900 used forexample, in semiconductor IC logic design, simulation, test, layout, andmanufacture. Design flow 900 includes processes, machines and/ormechanisms for processing design structures or devices to generatelogically or otherwise functionally equivalent representations of thedesign structures and/or devices described above and shown in FIGS. 1-8.The design structures processed and/or generated by design flow 900 maybe encoded on machine-readable transmission or storage media to includedata and/or instructions that when executed or otherwise processed on adata processing system generate a logically, structurally, mechanically,or otherwise functionally equivalent representation of hardwarecomponents, circuits, devices, or systems. Machines include, but are notlimited to, any machine used in an IC design process, such as designing,manufacturing, or simulating a circuit, component, device, or system.For example, machines may include: lithography machines, machines and/orequipment for generating masks (e.g. e-beam writers), computers orequipment for simulating design structures, any apparatus used in themanufacturing or test process, or any machines for programmingfunctionally equivalent representations of the design structures intoany medium (e.g. a machine for programming a programmable gate array).

Design flow 900 may vary depending on the type of representation beingdesigned. For example, a design flow 900 for building an applicationspecific IC (ASIC) may differ from a design flow 900 for designing astandard component or from a design flow 900 for instantiating thedesign into a programmable array, for example a programmable gate array(PGA) or a field programmable gate array (FPGA) offered by Altera® Inc.or Xilinx® Inc.

FIG. 9 illustrates multiple such design structures including an inputdesign structure 920 that is preferably processed by a design process910. Design structure 920 may be a logical simulation design structuregenerated and processed by design process 910 to produce a logicallyequivalent functional representation of a hardware device. Designstructure 920 may also or alternatively comprise data and/or programinstructions that when processed by design process 910, generate afunctional representation of the physical structure of a hardwaredevice. Whether representing functional and/or structural designfeatures, design structure 920 may be generated using electroniccomputer-aided design (ECAD) such as implemented by a coredeveloper/designer.

When encoded on a machine-readable data transmission, gate array, orstorage medium, design structure 920 may be accessed and processed byone or more hardware and/or software modules within design process 910to simulate or otherwise functionally represent an electronic component,circuit, electronic or logic module, apparatus, device, or system suchas those shown in FIGS. 1-8. As such, design structure 920 may comprisefiles or other data structures including human and/or machine-readablesource code, compiled structures, and computer-executable codestructures that when processed by a design or simulation data processingsystem, functionally simulate or otherwise represent circuits or otherlevels of hardware logic design. Such data structures may includehardware-description language (HDL) design entities or other datastructures conforming to and/or compatible with lower-level HDL designlanguages such as Verilog and VHDL, and/or higher level design languagessuch as C or C++.

Design process 910 preferably employs and incorporates hardware and/orsoftware modules for synthesizing, translating, or otherwise processinga design/simulation functional equivalent of the components, circuits,devices, or logic structures shown in FIGS. 1-8 to generate a Netlist980 which may contain design structures such as design structure 920.Netlist 980 may comprise, for example, compiled or otherwise processeddata structures representing a list of wires, discrete components, logicgates, control circuits, I/O devices, models, etc. that describes theconnections to other elements and circuits in an integrated circuitdesign. Netlist 980 may be synthesized using an iterative process inwhich netlist 980 is re-synthesized one or more times depending ondesign specifications and parameters for the device. As with otherdesign structure types described herein, netlist 980 may be recorded ona machine-readable data storage medium or programmed into a programmablegate array. The medium may be a non-volatile storage medium such as amagnetic or optical disk drive, a programmable gate array, a compactflash, or other flash memory. Additionally, or in the alternative, themedium may be a system or cache memory, buffer space, or electrically oroptically conductive devices and materials on which data packets may betransmitted and intermediately stored via the Internet, or othernetworking suitable means.

Design process 910 may include hardware and software modules forprocessing a variety of input data structure types including Netlist980. Such data structure types may reside, for example, within libraryelements 930 and include a set of commonly used elements, circuits, anddevices, including models, layouts, and symbolic representations, for agiven manufacturing technology (e.g., different technology nodes, 32 nm,45 nm, 90 nm, etc.). The data structure types may further include designspecifications 940, characterization data 950, verification data 960,design rules 970, and test data files 985 which may include input testpatterns, output test results, and other testing information. Designprocess 910 may further include, for example, standard mechanical designprocesses such as stress analysis, thermal analysis, mechanical eventsimulation, process simulation for operations such as casting, molding,and die press forming, etc. One of ordinary skill in the art ofmechanical design can appreciate the extent of possible mechanicaldesign tools and applications used in design process 910 withoutdeviating from the scope and spirit of the invention. Design process 910may also include modules for performing standard circuit designprocesses such as timing analysis, verification, design rule checking,place and route operations, etc.

Design process 910 employs and incorporates logic and physical designtools such as HDL compilers and simulation model build tools to processdesign structure 920 together with some or all of the depictedsupporting data structures along with any additional mechanical designor data (if applicable), to generate a second design structure 990.Design structure 990 resides on a storage medium or programmable gatearray in a data format used for the exchange of data of mechanicaldevices and structures (e.g., information stored in a IGES, DXF,Parasolid XT, JT, DRG, or any other suitable format for storing orrendering such mechanical design structures).

Similar to design structure 920, design structure 990 preferablycomprises one or more files, data structures, or other computer-encodeddata or instructions that reside on transmission or data storage mediaand that when processed by an ECAD system generate a logically orotherwise functionally equivalent form of one or more of the embodimentsof the invention shown in FIGS. 1-8. In one embodiment, design structure990 may comprise a compiled, executable HDL simulation model thatfunctionally simulates the device shown in FIGS. 1-8.

Design structure 990 may also employ a data format used for the exchangeof layout data of integrated circuits and/or symbolic data format (e.g.information stored in a GDSII (GDS2), GL1, OASIS, map files, or anyother suitable format for storing such design data structures). Designstructure 990 may comprise information such as, for example, symbolicdata, map files, test data files, design content files, manufacturingdata, layout parameters, wires, levels of metal, vias, shapes, data forrouting through the manufacturing line, and any other data required by amanufacturer or other designer/developer to produce a device orstructure as described above and shown in FIGS. 1-8. Design structure990 may then proceed to a stage 995 where, for example, design structure990: proceeds to tape-out, is released to manufacturing, is released toa mask house, is sent to another design house, is sent back to thecustomer, etc.

The resulting integrated circuit chips can be distributed by thefabricator in raw wafer form (that is, as a single wafer that hasmultiple unpackaged chips), as a bare die, or in a packaged form. In thelatter case the chip is mounted in a single chip package (such as aplastic carrier, with leads that are affixed to a motherboard or otherhigher level carrier) or in a multichip package (such as a ceramiccarrier that has either or both surface interconnections or buriedinterconnections). In any case the chip is then integrated with otherchips, discrete circuit elements, and/or other signal processing devicesas part of either (a) an intermediate product, such as a motherboard, or(b) an end product. The end product can be any product that includesintegrated circuit chips, ranging from toys and other low-endapplications to advanced computer products having a display, a keyboardor other input device, and a central processor.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”and/or “comprising,” when used in this specification, specify thepresence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

The corresponding structures, materials, acts, and equivalents of allmeans or step plus function elements that may be found in the claimsbelow are intended to include any structure, material, or act forperforming the function in combination with other claimed elements asspecifically claimed. The description of the present invention has beenpresented for purposes of illustration and description, but is notintended to be exhaustive or limited to the invention in the formdisclosed. Many modifications and variations will be apparent to thoseof ordinary skill in the art without departing from the scope and spiritof the invention. The embodiments were chosen and described in order tobest explain the principles of the invention and the practicalapplication, and to enable others of ordinary skill in the art tounderstand the invention for various embodiments with variousmodifications as are suited to the particular use contemplated.

As such, various modifications and adaptations may become apparent tothose skilled in the relevant arts in view of the foregoing description,when read in conjunction with the accompanying drawings and the appendedclaims. As but some examples, the various thicknesses, material types,dopant types and dopant concentrations are exemplary, and variations ofthe disclosed thicknesses, material types, dopant types and dopantconcentrations may be attempted by those skilled in the art. However,all such and similar modifications of the teachings of this inventionwill still fall within the scope of this invention.

1. A transistor structure, comprising: a channel disposed between asource and a drain; a gate conductor disposed over the channel andbetween the source and the drain; and a gate dielectric layer disposedbetween the gate conductor and the source, the drain and the channel;where the source and the drain are a raised source-drain and a lowerportion of the source and a lower portion of the drain that are adjacentto the channel are disposed beneath and in contact with the gatedielectric layer to define a source-drain extension region.
 2. Thetransistor structure of claim 1, further comprising a layer of oxide ornitride disposed around the gate conductor and over the source and thedrain, and a spacer layer disposed between the oxide layer and the gatedielectric layer, where said spacer layer is disposed but partially overthe source and the drain so as not to cover the lower portion of thesource and the drain that is adjacent to the channel.
 3. The transistorstructure of claim 1, where the channel is a portion of an extremelythin silicon on insulator layer, and where the source and the drain arean in-situ doped raised source and drain disposed upon the extremelythin silicon on insulator layer.
 4. The transistor structure of claim 1,where the gate dielectric layer is comprised of a high dielectricconstant material, and where the gate conductor is comprised of a metal.5. The transistor structure of claim 2, where the layer of oxide iscomprised of SiO₂, and where the spacer layer is comprised of Si₃N₄. 6.The transistor structure of claim 1, where an area of the lower portionof the source and the drain adjacent to the channel that is disposedbeneath and in contact with the gate dielectric layer is selected tooptimize a tradeoff between capacitance and resistance of thesource-drain extension region.
 7. The transistor structure of claim 1,fabricated in an extremely thin silicon on insulator wafer.
 8. Thetransistor structure of claim 3, where the source and drain are in-situdoped either p-type or n-type.
 9. The transistor structure of claim 1,embodied as a FinFET. 10.-19. (canceled)
 20. An integrated circuitcomprising a plurality of transistors, each of said transistorscomprising a channel disposed in a layer of silicon and disposed betweena raised source-drain structure, a gate conductor disposed over thechannel and between the source and the drain and a gate dielectric layerdisposed between the gate conductor and the source, the drain and thechannel; where said raised source-drain structure comprises a sourcefacet and a drain facet that upwardly slope away from channel, where anarea of the lower portion of the facet of the source and the facet ofthe drain that are covered by the gate dielectric layer define asource-drain extension region, and where the area of the lower portionof the facet of the source and the facet of the drain is selected tooptimize a tradeoff between capacitance and resistance of thesource-drain extension region.